Based on TrendForce's latest research into advanced semiconductor packaging, the push by GPU makers and hyperscale cloud service providers (CSPs) to develop increasingly powerful and versatile AI chips has made expanding package size a key focus of 2.5D packaging technology. Amid competition from Intel's EMIB-T, TSMC's CoWoS-L is projected to remain the dominant packaging solution for AI chips through 2028, thanks to its technical maturity and yield advantages.

Driven by robust AI demand, NVIDIA is aggressively advancing its integrated GB/VR rack solutions that consume higher chip volumes, with estimates suggesting its high-end GPU shipments could grow roughly 30% year-over-year in 2026. AMD is expected to counter with its MI400/MI450 series starting in the second half of 2026, boosting its overall shipment numbers. On the custom ASIC front, Google is set to lead the pack in 2026, with its TPU v7 expected to be the primary volume product. AWS is also ramping up its efforts, progressively transitioning its chip and AI server systems toward Trainium v3 in the latter half of 2026. Meanwhile, Microsoft and Meta continue to rely primarily on GPU-based servers, with their ASIC deployment plans currently on a smaller scale.

With AI chip demand surging and TSMC's packaging capacity stretched thin, Intel's EMIB-T technology could capture overflow orders. TrendForce notes that AI server chips have traditionally relied on TSMC's CoWoS-S packaging, which uses a silicon interposer to integrate HBM stacks with compute dies, delivering the performance required for generative AI applications. However, as chip sizes expand and HBM module counts rise, silicon interposer manufacturing is reaching physical limits. This necessitates a shift beyond just changing the interposer material to the CoWoS-L solution, which supports larger reticle exposure. CoWoS-L embeds high-speed silicon bridge chips within the interposer, offering greater flexibility in resolving the packaging and transmission challenges between compute dies and HBM.

Specifically, CoWoS-S technology, capable of integrating two SoCs or chiplets with eight HBM modules, will continue to be adopted by ASIC designs like Microsoft's Maia 200. However, when more SoCs, chiplets, and HBM modules need to be integrated, the CoWoS-L solution becomes necessary. Currently, NVIDIA and AMD AI accelerators already employ CoWoS-L, and beyond Meta's MTIA 400 slated for mass production in 2026, it is anticipated that AWS and Microsoft will also adopt CoWoS-L technology by 2027.

That said, CoWoS-L's larger interposer dimensions drive up packaging costs, and with TSMC's production capacity unable to meet demand, Intel's EMIB technology is emerging as an alternative. The EMIB approach reduces reliance on expensive interposers, potentially lowering overall costs, though its packaging performance is somewhat constrained by substrate routing density. To address this, Intel is enhancing its Line/Space and Microbump specifications while developing advanced solutions like EMIB-T, which incorporates TSVs to shorten signal paths and boost performance. TrendForce observes that Google could adopt EMIB-T packaging as early as 2027, and AWS is also currently evaluating EMIB technology. Although EMIB-T and CoWoS-L are competing approaches, considering technical maturity and yields, the latter is expected to remain the primary packaging technology for AI chips through 2028.